This started as an attempt to blink MIO through PL, but that’s not possible..
There is a schematic page named Z720_PL, showing the available, to the PL unit, pins.
These are called IO_*.
There is a schematic page named Z720_PS, showing the available, to the PL unit, pins.
These are called PS_DDR_* and PS_MIO_*.
They can also be seen under FIXED_IO and DDR entries inside the I/O Ports [tab] (after opening “Elaborate Design”).
I think EMIO serves as sharing PL’s pins to PS.
(I’m a bit unsure of the following, but):
The following are only accessible from the PS:
MIO50)MIO0/MIO9)MIO14/MIO15)